According to the experimental results, which were obtained for a whole test set of video sequences by using similar encoding configurations for all three examined representative encoders, H.265/MPEG-HEVC provides significant average bit-rate savings of 43.3% and 39.3% relative to VP9 and H.264/MPEG-AVC, respectively. This work presents a performance comparison of the two latest video coding standards H.264/MPEG-AVC and H.265/MPEG-HEVC (High-Efficiency Video Coding) as well as the recently published proprietary video coding scheme VP9. If videos are encoded with the low-delay configuration, BD-PSNR and BD-rate are equal to −0.026 dB and 1.64 %, respectively. The implemented algorithm is verified in the HM16 software.

Synthesis results show that the design can operate at 200 and 400 MHz when implemented in FPGA Arria II and TSMC 90 nm, respectively. As a consequence, a significant amount of computation is saved.

The search for rectangular PUs is performed only at the fractional-pel level and reuses partial costs computed for square PUs. The motion estimation for larger blocks is performed by the utilization of results of the 8 × 8 search. The integer-pel path supports test zone search for 8 × 8 prediction blocks. A separate interpolator for chroma additionally increases the throughput. In each clock cycle, the integer-pel and the fractional-pel path can evaluate one and four motion vectors for an 8 × 8 luma block, respectively. Access conflicts are avoided by the use of dual-port modules and register buffers for reused samples. The architecture embeds two parallel processing paths for the integer-pel and the fractional-pel motion estimation. The design allows the processing of videos at the clock frequency of 400 MHz. This paper presents the algorithm and the architecture of the high-throughput motion estimation system for the H.265/HEVC encoder.

Ffmpeg h265 encoding